US 12,271,305 B2
Two-level main memory hierarchy management
Sai Prashanth Muralidhara, Portland, OR (US); Alaa R. Alameldeen, Hillsboro, OR (US); Rajat Agarwal, Portland, OR (US); Wei P. Chen, Portland, OR (US); and Vivek Kozhikkottu, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2021, as Appl. No. 17/214,818.
Prior Publication US 2021/0216452 A1, Jul. 15, 2021
Int. Cl. G06F 12/0802 (2016.01); G06F 3/06 (2006.01)
CPC G06F 12/0802 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06F 2212/60 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a main memory comprising a first level main memory and a second level main memory, a cache line located in the first level main memory and an alias cache line located in the second level main memory, a requested data stored in only one of the cache line or the alias cache line, the cache line encoded with:
a location permutation tag to identify in which cache line location the requested data is stored, and
an access counter to determine if data stored in the cache line is hot or cold relative to data stored in the alias cache line;
the first level main memory and the second level main memory exposed to an operating system in a flat manner; and
a memory controller coupled to the main memory, the memory controller to:
read the location permutation tag in the cache line in the first level main memory to determine in which cache line location the requested data is stored,
update the access counter on every nth access to the cache line located in the first level main memory, and
read the access counter to determine whether to swap the requested data stored in the alias cache line with the data stored in the cache line.