| CPC G06F 11/1016 (2013.01) | 20 Claims |

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1. A data storage device comprising:
a memory; and
a processor configured to communicate with the memory and further configured to:
receive, from a host, an indication that data associated with a first logical address is correlated with data associated with a second logical address;
determine a correlation factor based on a degree of correlation between the data associated with the first logical address and the data associated with the second logical address; and
in response to the correlation factor being above a threshold:
store the data associated with the first logical address and the data associated with the second logical address in different regions of the memory having different bit error rates; and
use the data associated with the first logical address to assist in correcting an error in the data associated with the second logical address.
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