US 12,271,247 B2
System on chip controlling memory power using handshake process and operating method thereof
Jin-Ook Song, Seoul (KR); Yun-Ju Kwon, Yongin-si (KR); Dong-Sik Cho, Yongin-si (KR); and Byung-Tak Lee, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 2, 2023, as Appl. No. 18/500,563.
Application 18/500,563 is a continuation of application No. 17/827,847, filed on May 30, 2022, granted, now 11,836,029.
Application 17/827,847 is a continuation of application No. 16/670,026, filed on Oct. 31, 2019, granted, now 11,347,292, issued on May 31, 2022.
Application 16/670,026 is a continuation of application No. 15/677,050, filed on Aug. 15, 2017, granted, now 10,481,668, issued on Nov. 19, 2019.
Claims priority of application No. 10-2017-0009371 (KR), filed on Jan. 19, 2017.
Prior Publication US 2024/0061489 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3225 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01); G06F 15/78 (2006.01); G11C 5/14 (2006.01)
CPC G06F 1/3225 (2013.01) [G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 15/7821 (2013.01); G11C 5/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory connected to an external power source;
a memory controller configured to control the memory, output a memory access level indicating a frequency of accesses to the memory based on the accesses received from the memory controller, and inactivate a clock that is input to the memory controller based on a power adjustment signal; and
a power manager circuit configured to generate a control signal to manage a supply power level of the memory through a handshake with the memory controller, output a supply power control signal to the external power source, output the power adjustment signal including information to control the supply power level of the memory to the memory controller based on the memory access level.