US 12,271,220 B1
Managing multi-phase clock signals for integrated circuit devices
David Carlson, Haslet, TX (US); and Saptadeep Pal, Cupertino, CA (US)
Assigned to Auradine, Inc., Santa Clara, CA (US)
Filed by Auradine, Inc., Santa Clara, CA (US)
Filed on Jun. 30, 2023, as Appl. No. 18/345,725.
Int. Cl. G06F 1/06 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/06 (2013.01); G06F 1/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a clock signal generator configured to generate a reference clock signal; and
a plurality of processing units coupled to the clock signal generator, at least one of the plurality of processing units comprising:
a phase generator configured to selectively generate at least two sets of multi-phase clock signals based on the reference clock signal and corresponding control signals, the at least two sets of multi-phase clock signals having different respective frequencies; and
a computation unit configured to perform at least one computing function based on a selected one of the at least two sets of multi-phase clock signals.