US 12,271,107 B2
Method of manufacturing integrated circuit
Hsu-Ting Huang, Hsinchu (TW); Shih-Hsiang Lo, Hsinchu (TW); and Ru-Gun Liu, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Feb. 29, 2024, as Appl. No. 18/591,383.
Application 18/591,383 is a continuation of application No. 17/878,719, filed on Aug. 1, 2022, granted, now 11,947,254.
Application 17/878,719 is a continuation of application No. 17/195,469, filed on Mar. 8, 2021, granted, now 11,415,890, issued on Aug. 16, 2022.
Application 17/195,469 is a continuation of application No. 16/144,882, filed on Sep. 27, 2018, granted, now 10,942,443, issued on Mar. 9, 2021.
Claims priority of provisional application 62/586,697, filed on Nov. 15, 2017.
Prior Publication US 2024/0201579 A1, Jun. 20, 2024
Int. Cl. G03F 1/36 (2012.01); G03F 1/78 (2012.01); G03F 7/20 (2006.01)
CPC G03F 1/36 (2013.01) [G03F 7/2061 (2013.01); G03F 1/78 (2013.01)] 20 Claims
 
1. A method of manufacturing an integrated circuit comprising:
calibrating an optical proximity correction (OPC) model by adjusting a first parameter and a second parameter, the first parameter including an effect caused by an electron-beam lithography tool for making a photomask, and the second parameter including one or more of a geometric feature of a structure and a manufacturing process to make the structure;
calculating a grid pattern density map of a device layout;
generating a correction map from at least the calibrated OPC model and the grid pattern density map of the device layout;
performing an OPC to generate an optimized mask layout from at least the generated correction map and the calibrated OPC model;
manufacturing a photomask from at least the optimized mask layout; and
manufacturing the integrated circuit by a process comprising photolithography employing the photomask.