US 12,270,852 B2
Method and system for wafer-level testing
Jun He, Hsinchu (TW); Yu-Ting Lin, Hsin-Chu (TW); Wei-Hsun Lin, Hsinchu County (TW); Yung-Liang Kuo, Hsinchu (TW); and Yinlung Lu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on May 23, 2024, as Appl. No. 18/672,047.
Application 18/672,047 is a continuation of application No. 18/301,274, filed on Apr. 17, 2023, granted, now 12,025,655.
Application 18/301,274 is a continuation of application No. 17/353,543, filed on Jun. 21, 2021, granted, now 11,630,149, issued on Apr. 18, 2023.
Application 17/353,543 is a continuation of application No. 16/522,551, filed on Jul. 25, 2019, granted, now 11,073,551, issued on Jul. 27, 2021.
Claims priority of provisional application 62/719,044, filed on Aug. 16, 2018.
Prior Publication US 2024/0310434 A1, Sep. 19, 2024
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2879 (2013.01) [G01R 31/2886 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period; and
applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage, wherein the stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.