US 12,269,029 B2
Pressure-driven fluidic logic gate
Nazek Mohamad El-Atab, Thuwal (SA); and Javier Eduardo Chavarrio Canas, Thuwal (SA)
Assigned to KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY, Thuwal (SA)
Filed by KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY, Thuwal (SA)
Filed on Aug. 18, 2020, as Appl. No. 16/996,128.
Claims priority of provisional application 62/892,655, filed on Aug. 28, 2019.
Prior Publication US 2021/0060552 A1, Mar. 4, 2021
Int. Cl. B01L 3/00 (2006.01)
CPC B01L 3/502707 (2013.01) [B01L 3/502715 (2013.01); B01L 3/50273 (2013.01); B01L 2200/027 (2013.01); B01L 2300/0816 (2013.01); B01L 2300/0887 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A microfluidic chip comprising:
a substrate;
plural layers located on top of each other over the substrate;
a top layer located over the plural layers so that the plural layers are sandwiched between the substrate and the top layer;
a first input port formed into the top layer;
a second input port formed into the top layer;
a first output port formed into a first layer of the plural layers;
a second output port formed into a second layer of the plural layers; and
plural microchannels configured to fluidly connect the first input port and the second input port to each of the first output port and the second output port so that, when a fluid is injected at the first and/or the second input ports, the fluid moves vertically down and then vertically upward through the plural microchannels, to reach the second output port,
wherein the second layer is located over the first layer, and
wherein the first and second output ports are directly exposed to an ambient of the microfluidic chip.