US 11,950,456 B2
Array substrate and display device
Yipeng Chen, Beijing (CN); Ling Shi, Beijing (CN); Wenqiang Li, Beijing (CN); Shuai Xie, Beijing (CN); and Yang Yu, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/437,936
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Oct. 27, 2020, PCT No. PCT/CN2020/124163
§ 371(c)(1), (2) Date Sep. 10, 2021,
PCT Pub. No. WO2022/087851, PCT Pub. Date May 5, 2022.
Prior Publication US 2022/0328589 A1, Oct. 13, 2022
Int. Cl. H10K 59/121 (2023.01); H10K 59/131 (2023.01)
CPC H10K 59/1213 (2023.02) [H10K 59/131 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An array substrate comprising:
a pixel driving circuit and a data line, wherein the pixel driving circuit comprises a driving transistor, a first transistor connected between a first electrode of the driving transistor and the data line, a second transistor connected between a gate electrode and a second electrode of the driving transistor, the driving transistor and the first transistor are P-type transistors, and the second transistor is a N-type transistor; and
a base substrate and a first conductive layer arranged at a side of the base substrate, the base substrate comprising:
a first conductive portion for forming the gate electrode of the driving transistor;
a first gate line at a side of the first conductive portion, a part of the first gate line being configured to form a gate electrode of the first transistor; and
a second gate line at a side of the first gate line away from the first conductive portion, a part of the second gate line being configured to form a first gate electrode of the second transistor.