US 11,950,427 B2
Ferroelectric memory device and method of forming the same
Chun-Chieh Lu, Taipei (TW); Sai-Hooi Yeong, Zhubei (TW); Bo-Feng Young, Taipei (TW); Yu-Ming Lin, Hsinchu (TW); and Chih-Yu Chang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 21, 2022, as Appl. No. 17/869,824.
Application 17/869,824 is a division of application No. 17/108,218, filed on Dec. 1, 2020, granted, now 11,515,332.
Claims priority of provisional application 63/031,033, filed on May 28, 2020.
Prior Publication US 2022/0359570 A1, Nov. 10, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 21/383 (2006.01); H01L 21/425 (2006.01); H01L 21/477 (2006.01); H01L 29/24 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 21/02565 (2013.01); H01L 21/383 (2013.01); H01L 21/425 (2013.01); H01L 21/477 (2013.01); H01L 29/24 (2013.01); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory cell comprising:
a transistor over a semiconductor substrate, the transistor comprising:
a ferroelectric layer arranged along a sidewall of a word line, the ferroelectric layer comprising a species with valence of 5, valence of 7, or a combination thereof; and
an oxide semiconductor layer electrically coupled to a source line and a bit line, wherein the ferroelectric layer is disposed between the oxide semiconductor layer and the word line.