US 11,950,426 B2
Memory device having 2-transistor vertical memory cell and wrapped data line structure
Kamal M. Karda, Boise, ID (US); Eric S. Carman, San Francisco, CA (US); Karthik Sarpatwari, Boise, ID (US); Durai Vishak Nirmal Ramaswamy, Boise, ID (US); Richard E Fackenthal, Carmichael, CA (US); and Haitao Liu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 27, 2023, as Appl. No. 18/126,679.
Application 18/126,679 is a division of application No. 17/514,979, filed on Oct. 29, 2021, granted, now 11,616,073.
Prior Publication US 2023/0240077 A1, Jul. 27, 2023
Int. Cl. H10B 43/50 (2023.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01)
CPC H10B 43/50 (2023.02) [H01L 29/1062 (2013.01); H01L 29/42396 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first transistor and a second transistor of a memory cell, such that the first transistor includes a first channel region, and a charge storage structure separated from the first channel region by a first dielectric material, and the second transistor includes a second channel region formed over the charge storage structure;
forming a trench in a second dielectric material adjacent the first channel region, such that the trench is separated from the first channel region by a portion of the second dielectric material; and
forming a data line over the first and second channel regions, such that the data line includes a portion in the trench.