US 11,950,413 B2
High voltage polysilicon gate in high-K metal gate device
Meng-Han Lin, Hsinchu (TW); and Te-Hsin Chiu, Miaoli County (TW)
Assigned to Taiwan SemiconductorManufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Dec. 13, 2022, as Appl. No. 18/079,971.
Application 18/079,971 is a continuation of application No. 16/535,431, filed on Aug. 8, 2019, granted, now 11,569,251.
Prior Publication US 2023/0109700 A1, Apr. 13, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H10B 41/40 (2023.01)
CPC H10B 41/40 (2023.02) [H01L 21/26513 (2013.01); H01L 21/28052 (2013.01); H01L 21/3212 (2013.01); H01L 21/32139 (2013.01); H01L 27/0207 (2013.01); H01L 29/0847 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/42364 (2013.01); H01L 29/42376 (2013.01); H01L 29/4933 (2013.01); H01L 29/665 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66575 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a semiconductor substrate comprising a first area and a second area;
a polysilicon gate formed in the first area, wherein the polysilicon gate comprises a polysilicon electrode and a gate dielectric layer between the polysilicon electrode and the semiconductor substrate;
a high-κ metal gate formed in the second area, wherein the high-κ metal gate comprises a metal electrode and a high-κ dielectric layer between the metal electrode and the semiconductor substrate; and
wherein the polysilicon electrode has a width that is greater than a width of the metal electrode;
the polysilicon gate is a high voltage gate having a threshold voltage higher than the high-κ metal gate;
the gate dielectric layer is thicker than the high-κ dielectric layer; and
upper surfaces of the polysilicon electrode and the metal electrode are coplanar.