US 11,950,361 B2
Method and procedure for miniaturing a multi-layer PCB
Shaun Joseph Greaney, Freehold, NJ (US); Robert Migliorino, Wayne, NJ (US); Michael Liccone, Scotch Plains, NJ (US); and Clint Smith, Warwick, NY (US)
Assigned to VEEA INC., New York, NY (US)
Filed by Veea Inc., New York, NY (US)
Filed on Sep. 16, 2022, as Appl. No. 17/946,450.
Application 17/946,450 is a division of application No. 17/313,073, filed on May 6, 2021, granted, now 11,523,502.
Claims priority of provisional application 63/020,745, filed on May 6, 2020.
Prior Publication US 2023/0017840 A1, Jan. 19, 2023
Int. Cl. H05K 1/02 (2006.01)
CPC H05K 1/0298 (2013.01) [H05K 1/0218 (2013.01); H05K 1/0231 (2013.01); H05K 1/0242 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A multi-layer printed circuit board (PCB), comprising: a plurality of layers comprising:
a plurality of signal layers,
a plurality of ground plane layers,
a plurality of inner signal layers, and
a single core substrate layer,
wherein:
each individual layer in the plurality of layers is separated from its immediately adjacent layers by one or more prepreg substrate layers,
each of the one or more prepeg substrate layers is less rigid than the single core substrate layer,
the one or more prepeg substrate layers bond two or more of the prepreg separated individual layers together, and
the prepreg-separated individual layers include the plurality of signal layers, the plurality of ground plane layers, and the plurality of inner signal layers.