CPC H04W 92/18 (2013.01) [H04L 1/1854 (2013.01)] | 11 Claims |
1. A device comprising:
a processor circuit and a memory circuit, wherein the memory is arranged to store instructions for the processor circuit,
wherein the processor circuit is arranged to communicate using a portion of a plurality of sidelink resources,
wherein the processor circuit is arranged to receive a sidelink feedback from a receiving device for a plurality of data transmissions,
wherein the sidelink feedback indicates a successful or non-successful reception by the receiving device,
wherein the processor circuit is arranged to bundle a plurality of sidelink feedbacks,
wherein the bundle is reported to a third device.
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