CPC H04W 72/20 (2023.01) [H04W 92/18 (2013.01)] | 20 Claims |
1. A terminal device, comprising: a processor, a memory, and a transceiver, wherein the memory is configured to store computer program, the transceiver is configured to communicate with another device, and the processor is configured to implement the computer program in the memory to:
control the transceiver to receive Downlink Control Information (DCI);
determine a format of the DCI; when the DCI is a DCI in a first format, the DCI is used for scheduling a first type of sidelink; when the DCI is a DCI in a second format, the DCI is used for scheduling a second type of sidelink; and
control the transceiver to transmit sidelink data by using a scheduled sidelink;
wherein the second type of sidelink supports a larger bandwidth than the first type of sidelink;
the first type of sidelink supports only one kind of subcarrier spacing, and the second type of sidelink is capable of supporting multiple kinds of subcarrier spacing.
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