US 11,949,604 B2
Integrated network switch operation
Renato J. Recio, Austin, TX (US); Eran Gampel, Tel Aviv (IL); Claude Basso, Nice (FR); Gal Sagi, Hod Hasharon (IL); and Guy Laden, Tel Aviv (IL)
Assigned to Inernational Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Oct. 6, 2021, as Appl. No. 17/450,097.
Prior Publication US 2023/0108374 A1, Apr. 6, 2023
Int. Cl. H04L 12/879 (2013.01); H04L 49/00 (2022.01); H04L 49/90 (2022.01)
CPC H04L 49/9026 (2013.01) [H04L 49/3027 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated P4 switching device comprising a processor coupled to a computer-readable memory unit, the memory unit comprising instructions that when executed by the processor implements a network state processing method comprising:
detecting, by said processor, operational states for ports of a server Internet protocol (IP) data plane component;
analyzing, by said processor, each operational state of said operational states;
generating, by said processor based on results of said analyzing, matching and action rules associated with said operational states with respect to data packets arriving at said ports;
storing, by said processor, data describing each said operational state within at least one port cache structure for at least one port of said ports;
detecting, by said processor, an incoming data packet at a first port of said ports;
distributing, by said processor, said matching and action rules between port engines of said ports and said processor;
executing, by said processor in response to said detecting and said distributing, said matching and action rules with respect to said incoming data packet;
transmitting, by said processor in response to results of said executing, said incoming data packet to a destination port of said ports;
enabling, by said processor, operational functionality of said integrated P4 switching device with respect to execution of said incoming data packet at said destination port, wherein said integrated P4 switching device comprises said ports, said at least one port cache structure, and said port engines; and
distributing, by said processor, Internet Protocol (IP) network state processing and storage (i) between said port engines and said cache structures associated with the port engines at said ports and a centralized P4/central processing unit (CPU) processing unit that utilizes external memory shared across switch ports or (ii) between a decentralized P4 based pipeline per ort, a centralized P4 pipeline, and a software based rules based processing pipeline that runs in external or embedded central processing unit (CPU) cores.