US 11,949,539 B2
Burst-tolerant decision feedback equalization
Thomas J. Giovannini, San Jose, CA (US); and Abhijit Abhyankar, Sunnyvale, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Nov. 1, 2021, as Appl. No. 17/516,502.
Application 17/516,502 is a continuation of application No. 16/418,358, filed on May 21, 2019, granted, now 11,184,197.
Application 16/418,358 is a continuation of application No. 15/570,703, granted, now 10,320,591, issued on Jun. 11, 2019, previously published as PCT/US2016/043534, filed on Jul. 22, 2016.
Claims priority of provisional application 62/304,834, filed on Mar. 7, 2016.
Claims priority of provisional application 62/197,799, filed on Jul. 28, 2015.
Prior Publication US 2022/0123969 A1, Apr. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 25/03 (2006.01); G06F 3/05 (2006.01); G06F 3/06 (2006.01); G11C 19/00 (2006.01)
CPC H04L 25/03057 (2013.01) [G06F 3/05 (2013.01); G06F 3/0604 (2013.01); G06F 3/0644 (2013.01); G06F 3/0673 (2013.01); G11C 19/00 (2013.01); H04L 25/03146 (2013.01); H04L 25/03878 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method of operation within an integrated-circuit buffer component (buffer IC), the method comprising:
sampling a signaling link during each of a sequence of sampling intervals to generate a corresponding sequence of data bits, including resolving each of the data bits to a logic state according to voltage levels, during the sampling interval, of both the signaling link and an equalization signal;
generating the equalization signal for each of the sampling intervals based on either (i) the logic state of one or more previously generated data bits or (ii) one or more bit values having predetermined logic states, depending on whether the sampling interval is preceded by a time period in which no data is conveyed to the buffer IC via the signaling link; and
outputting the sequence of data bits from the buffer IC to a memory component.