US 11,949,419 B2
Delay adjustment circuits
Maksim Kuzmenka, Munich (DE); and Elena Cabrera Bernal, Munich (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 19, 2022, as Appl. No. 18/084,172.
Application 18/084,172 is a continuation of application No. 17/351,421, filed on Jun. 18, 2021, granted, now 11,563,427.
Prior Publication US 2023/0119349 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 5/13 (2014.01); G11C 11/22 (2006.01); G11C 11/4076 (2006.01); H03F 3/45 (2006.01); H03G 3/30 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/13 (2013.01) [G11C 11/2293 (2013.01); G11C 11/4076 (2013.01); H03F 3/45179 (2013.01); H03G 3/30 (2013.01); G11C 11/221 (2013.01); H03K 2005/00019 (2013.01); H03K 2005/00208 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a set of signal lines; and
a circuit configured to provide a load on the set of signal lines associated with a set of signals of a multi-phase clock, the circuit comprising:
a set of amplifiers each having a respective input coupled with a corresponding signal line of the set of signal lines, the set of amplifiers having respective gains at nodes of the set of amplifiers relative to the respective inputs;
a sub-circuit coupled with the set of amplifiers and configured to control the respective gains of the set of amplifiers; and
a second circuit having a set of inputs coupled with the set of signal lines, the second circuit coupled with the sub-circuit and configured to control the sub-circuit based on signals detected on the set of inputs.