US 11,949,320 B2
Rdson-based current sensing system
Vishnuvardhan Reddy Jaladanki, Secunderabad (IN); Preetam Charan Anand Tadeparthy, Bengaluru (IN); Scott Ragona, Bethlehem, PA (US); Rengang Chen, Center Valley, PA (US); Evan Michael Reutzel, Center Valle, PA (US); and Bhaskar Ramachandran, Coimbatore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 23, 2022, as Appl. No. 17/678,220.
Claims priority of provisional application 63/152,702, filed on Feb. 23, 2021.
Prior Publication US 2022/0271664 A1, Aug. 25, 2022
Int. Cl. H02M 3/158 (2006.01); H02M 1/00 (2006.01)
CPC H02M 1/0009 (2021.05) [H02M 3/158 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a switch having a first terminal and a second terminal, the second terminal configured to switch between a ground terminal or a low-side power transistor based on a control signal;
a first current path and a second current path, the first current path having a current path output coupled to the second terminal of the switch, the second current path having a current path output coupled to the ground terminal, and each of the first and second current paths including:
a respective transistor having a control terminal, a first current terminal coupled to an input of the current path, and a second current terminal;
a respective differential amplifier having a positive input, a negative input coupled to the second current terminal, and an output coupled to the control terminal;
a respective variable resistor coupled between the negative input and the current path output;
a current mirror having an input coupled to the input of the first current path, a first output coupled to the input of the second current path, and a second output;
a first buffer having an input and an output, the input of the first buffer coupled to the second output of the current mirror;
a second buffer having an input and an output; and
a third variable resistor coupled between the output of the second buffer and the input of the first buffer.