US 11,949,022 B2
Three dimensional memory
Zhenyu Lu, Boise, ID (US); Hongbin Zhu, Boise, ID (US); Gordon A. Haller, Boise, ID (US); Roger W. Lindsay, Boise, ID (US); Andrew Bicksler, Nampa, ID (US); Brian J. Cleereman, Boise, ID (US); and Minsoo Lee, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 23, 2022, as Appl. No. 17/678,971.
Application 17/678,971 is a division of application No. 16/845,793, filed on Apr. 10, 2020, granted, now 11,289,611.
Application 16/845,793 is a division of application No. 13/716,287, filed on Dec. 17, 2012, granted, now 10,651,315, issued on May 12, 2020.
Prior Publication US 2022/0181483 A1, Jun. 9, 2022
Int. Cl. H01L 29/788 (2006.01); H01L 21/285 (2006.01); H01L 23/535 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H01L 29/788 (2013.01) [H01L 21/28518 (2013.01); H01L 23/535 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/792 (2013.01); H01L 29/7926 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 12 Claims
OG exemplary drawing
 
1. An electronic system comprising:
supervisory circuitry to generate memory control commands; and
at least one memory, coupled to the supervisory circuitry, to respond to the memory control commands, the at least one memory comprising:
at least one source line over an upper surface of a substrate, the at least one source line having a vertical thickness and consisting of a heavily doped metallic silicide throughout the vertical thickness; and
two or more vertical NAND flash strings with select gates disposed over the source line, each of the two or more vertical NAND flash strings comprising insulating layers, conductive layers, and a pillar of semiconductor material extending through the insulating layers and conductive layers, and partially through one source line of the at least one source line, the pillar being in ohmic contact with the one source line.