US 11,948,989 B2
Gate-all-around device with protective dielectric layer and method of forming the same
Cheng-Ting Chung, Hsinchu (TW); Yi-Bo Liao, Hsinchu (TW); Hou-Yu Chen, Hsinchu County (TW); and Kuan-Lun Cheng, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Mar. 21, 2022, as Appl. No. 17/699,303.
Application 17/699,303 is a continuation of application No. 16/583,485, filed on Sep. 26, 2019, granted, now 11,282,935.
Prior Publication US 2022/0208982 A1, Jun. 30, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/3212 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/401 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a stack of semiconductor layers over a substrate, the stack of semiconductor layers including a first semiconductor layer and a second semiconductor layer;
forming a protective dielectric layer directly on the second semiconductor layer, wherein the forming of the protective dielectric layer directly on the second semiconductor layer includes:
forming a hard mask on the protective dielectric layer;
patterning the protective dielectric layer and the stack of semiconductor layers while using the hard mask as a mask; and
removing the hard mask;
forming a first gate dielectric layer directly on the protective dielectric layer;
removing the first gate dielectric layer to expose the protective dielectric layer;
removing a first portion of the second semiconductor layer;
forming a second gate dielectric layer directly on the protective dielectric layer and the first semiconductor layer; and
forming a gate electrode around the second gate dielectric layer.