US 11,948,974 B2
Semiconductor device including vertical transistor with back side power structure
Shih-Wei Peng, Hsinchu (TW); Te-Hsin Chiu, Hsinchu (TW); and Jiann-Tyng Tzeng, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/461,476.
Prior Publication US 2023/0069119 A1, Mar. 2, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 23/522 (2006.01); H01L 25/11 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 23/5226 (2013.01); H01L 25/115 (2013.01); H01L 29/0649 (2013.01); H01L 29/42392 (2013.01); H01L 29/78618 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a gate structure including a gate pad and a gate contact on the gate pad;
a first source region disposed below the gate pad, wherein the first source region comprises a first source pad;
a first drain region disposed on the gate pad, wherein the first drain region comprises a first drain pad, and wherein the first source region, the first drain region and the gate structure form a first transistor;
a second source region disposed below the gate pad, wherein the second source region comprises a second source pad;
a second drain region disposed on the gate pad, wherein the second drain region comprises a second drain pad, and wherein the second source region, the second drain region and the gate structure form a second transistor; and
at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply;
a plurality of first vias formed through the gate pad and connecting the first drain pad with the first source pad; and
a plurality of second vias formed through the gate pad and connecting the second drain pad with the second source pad.