US 11,948,973 B2
Gate-all-around field-effect transistor device
Kuo-Cheng Chiang, Zhubei (TW); Huan-Chieh Su, Tianzhong Township (TW); Shi Ning Ju, Hsinchu (TW); Kuan-Ting Pan, Taipei (TW); and Chih-Hao Wang, Baoshan Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 16, 2021, as Appl. No. 17/402,985.
Application 17/402,985 is a continuation of application No. 16/550,049, filed on Aug. 23, 2019, granted, now 11,114,529.
Prior Publication US 2021/0376081 A1, Dec. 2, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/0673 (2013.01) [H01L 21/02532 (2013.01); H01L 21/0262 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 29/0847 (2013.01); H01L 29/0886 (2013.01); H01L 29/1033 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/495 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming semiconductor strips protruding above a substrate;
forming isolation regions between adjacent ones of the semiconductor strips;
forming hybrid fins on the isolation regions;
forming a dummy gate structure over the semiconductor strips and the hybrid fins, wherein first portions of the hybrid fins are directly under the dummy gate structure, and second portions of the hybrid fins are beyond boundaries of the dummy gate structure;
forming source/drain regions over the semiconductor strips on opposing sides of the dummy gate structure;
removing the dummy gate structure;
forming nanowires over the semiconductor strips between the source/drain regions, wherein the nanowires are over and aligned with respective semiconductor strips; and
after forming the nanowires, reducing widths of the first portions of the hybrid fins while keeping widths of the second portions of the hybrid fins unchanged.