US 11,948,972 B2
High-voltage nano-sheet transistor
Yu-Xuan Huang, Hsinchu (TW); Chia-En Huang, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); Kuan-Lun Cheng, Hsin-Chu (TW); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 30, 2020, as Appl. No. 16/916,951.
Prior Publication US 2021/0408234 A1, Dec. 30, 2021
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 20/20 (2023.01)
CPC H01L 29/0673 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H10B 20/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A structure, comprising:
a substrate;
a stack of first and second nano-sheet layers disposed on the substrate, wherein the first and second nano-sheet layers are arranged in an alternating configuration, and wherein the first nano-sheet layers are narrower than the second nano-sheet layers;
an epitaxial structure abutting end-portions of the stack of first and second nano-sheet layers;
a spacer structure interposed between the first nano-sheet layers and the epitaxial structure;
a gate structure on a top surface and sidewall surfaces of the stack of first and second nano-sheet layers wherein the gate structure comprises:
a first dielectric disposed on a top surface of one of the second nano-sheet layers and in contact with the epitaxial structure, wherein sidewalls of the first dielectric are aligned with sidewalls of the one of the second nano-sheet layers; and
a second dielectric disposed on the first dielectric and thinner than the first dielectric; and
gate spacers disposed on and in contact with a top surface of the first dielectric.