US 11,948,971 B2
Confined source/drain epitaxy regions and method forming same
Jeng-Wei Yu, New Taipei (TW); Tsz-Mei Kwok, Hsinchu (TW); Tsung-Hsi Yang, Zhubei (TW); Li-Wei Chou, Hsinchu (TW); and Ming-Hua Yu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2021, as Appl. No. 17/398,741.
Application 17/398,741 is a division of application No. 16/458,637, filed on Jul. 1, 2019, granted, now 11,101,347.
Claims priority of provisional application 62/773,013, filed on Nov. 29, 2018.
Prior Publication US 2021/0376073 A1, Dec. 2, 2021
Int. Cl. H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/78651 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a semiconductor substrate;
isolation regions over a bulk portion of the semiconductor substrate;
a semiconductor strip between opposite portions of the isolation regions;
a first dielectric fin and a second dielectric fin on opposite sides of the semiconductor strip, wherein the first dielectric fin and the second dielectric fin overlap, and are physically joined to, a first isolation region and a second isolation, respectively, of the isolation regions;
a semiconductor region over and contacting the semiconductor strip, wherein the semiconductor region extends laterally beyond edges of the semiconductor strip to contact the first dielectric fin and the second dielectric fin; and
an air gap between the semiconductor region and the first dielectric fin.