US 11,948,942 B2
Integrated circuit device
Minhee Choi, Suwon-si (KR); Keunhwi Cho, Seoul (KR); Myunggil Kang, Suwon-si (KR); Seokhoon Kim, Suwon-si (KR); Dongwon Kim, Seongnam-si (KR); Pankwi Park, Incheon (KR); and Dongsuk Shin, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 16, 2023, as Appl. No. 18/122,253.
Application 18/122,253 is a continuation of application No. 17/231,114, filed on Apr. 15, 2021, granted, now 11,631,674.
Claims priority of application No. 10-2020-0101392 (KR), filed on Aug. 12, 2020.
Prior Publication US 2023/0223405 A1, Jul. 13, 2023
Int. Cl. H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/161 (2006.01); H01L 29/167 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/0262 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/167 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a fin-type active area along a first horizontal direction on a substrate;
a nanosheet stack including at least one nanosheet on a fin top of the fin-type active area, the at least one nanosheet being spaced apart from the fin top in a vertical direction;
a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure surrounding the at least one nanosheet; and
a source/drain area on the fin-type active area, the source/drain area contacting the at least one nanosheet, and the source/drain area including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area,
wherein each of the outer blocking layer and the main body layer includes a Si1-xGex layer, where x≠0, and the inner blocking layer includes a Si layer, and
wherein a level of a lowermost surface of the source/drain area is lower than a level of the fin top in the vertical direction.