US 11,948,941 B2
Semiconductor device, integrated circuit and methods of manufacturing the same
Yi-Tse Hung, Hsinchu (TW); Ang-Sheng Chou, Hsinchu (TW); Hung-Li Chiang, Taipei (TW); Tzu-Chiang Chen, Hsinchu (TW); and Chao-Ching Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 23, 2021, as Appl. No. 17/355,206.
Claims priority of provisional application 63/156,935, filed on Mar. 5, 2021.
Prior Publication US 2022/0285345 A1, Sep. 8, 2022
Int. Cl. H01L 29/417 (2006.01); H01L 21/8238 (2006.01); H01L 23/367 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 29/24 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 23/367 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/1033 (2013.01); H01L 29/24 (2013.01); H01L 29/41775 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate layer, disposed over and electrically coupled to a substrate;
a channel material layer, disposed over the gate layer, wherein a material of the channel material layer comprises a first low dimensional material;
a first dielectric layer, sandwiched between the gate layer and the channel material layer, wherein sidewalls of the gate layer is free of the first dielectric layer; and
source/drain terminals, in contact with the channel material layer, wherein the channel material layer is at least partially sandwiched between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.