US 11,948,936 B2
Forming ESD devices using multi-gate compatible processess
Chih-Hung Wang, Hsinchu (TW); Chih Chieh Yeh, Taipei (TW); Zi-Ang Su, Taoyuan County (TW); Chia-Ju Chou, Taipei (TW); and Ming-Shuan Li, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Apr. 24, 2023, as Appl. No. 18/305,556.
Application 18/305,556 is a continuation of application No. 17/224,671, filed on Apr. 7, 2021, granted, now 11,637,099.
Claims priority of provisional application 63/039,293, filed on Jun. 15, 2020.
Prior Publication US 2023/0268337 A1, Aug. 24, 2023
Int. Cl. H01L 27/02 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/0266 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 27/0296 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a fin disposed in a first region of the semiconductor device, the fin having first type epitaxial layers and second type epitaxial layers alternatingly disposed in a vertical direction, the first type epitaxial layers having a first material composition and the second type epitaxial layers having a second material composition different from the first material composition;
a plurality of channel members disposed in a second region of the semiconductor device and stacked in the vertical direction, the channel members having the first material composition;
first and second metal gates disposed on a top surface of the fin;
a third metal gate wrapping around each of the channel members;
a first implant region in the fin, wherein the first implant region has a first conductivity type; and
a second implant region in the fin, wherein the second implant region has a second conductivity type opposite the first conductivity type.