US 11,948,926 B2
Integrated circuit package and method
Chen-Hua Yu, Hsinchu (TW); Wei Ling Chang, Hsinchu (TW); Chuei-Tang Wang, Taichung (TW); and Chieh-Yen Chen, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/854,386.
Application 17/854,386 is a continuation of application No. 16/882,054, filed on May 22, 2020, granted, now 11,387,222.
Claims priority of provisional application 62/923,161, filed on Oct. 18, 2019.
Prior Publication US 2022/0336431 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/16 (2023.01); H01L 23/00 (2006.01)
CPC H01L 25/16 (2013.01) [H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 2924/12 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a processor die comprising logic devices;
a first memory die directly face-to-face bonded to the processor die by metal-to-metal bonds and by dielectric-to-dielectric bonds;
a first dielectric layer laterally surrounding the first memory die; and
a first redistribution structure over the first dielectric layer and the first memory die, a sidewall of the first redistribution structure being laterally coterminous with a sidewall of the processor die and with a sidewall of the first dielectric layer, the first redistribution structure comprising metallization patterns electrically coupled to the first memory die and the processor die.