US 11,948,914 B2
Chip package structure with integrated device integrated beneath the semiconductor chip
Feng-Cheng Hsu, New Taipei (TW); Shin-Puu Jeng, Hsinchu (TW); and Shuo-Mao Chen, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 20, 2022, as Appl. No. 17/813,648.
Application 17/813,648 is a continuation of application No. 16/922,132, filed on Jul. 7, 2020, granted, now 11,404,394.
Claims priority of provisional application 62/897,458, filed on Sep. 9, 2019.
Prior Publication US 2022/0367411 A1, Nov. 17, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 24/13 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H01L 2924/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a package substrate;
a semiconductor chip disposed over the package substrate, wherein the semiconductor chip has a lower surface facing the package substrate and is electrically connected to the package substrate through conductive structures; and
an integrated device located below and bonded to the lower surface of the semiconductor chip, wherein the integrated device is laterally surrounded by the conductive structures, and the integrated device and the conductive structures are located within boundaries of the semiconductor chip when viewed in a direction perpendicular to the lower surface of the semiconductor chip,
wherein the package substrate has an upper surface facing the lower surface of the semiconductor chip and a cavity formed on the upper surface, wherein the cavity is configured to accommodate the integrated device.