US 11,948,898 B2
Etch barrier for microelectronic packaging conductive structures
Kristof Darmawikarta, Chandler, AZ (US); Srinivas V. Pietambaram, Chandler, AZ (US); Hongxia Feng, Chandler, AZ (US); Xiaoying Guo, Chandler, AZ (US); and Benjamin T. Duong, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 16, 2019, as Appl. No. 16/413,943.
Prior Publication US 2020/0365534 A1, Nov. 19, 2020
Int. Cl. H01L 23/66 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/66 (2013.01) [H01L 21/76825 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76879 (2013.01); H01L 23/5283 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 2223/6605 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An integrated circuit package comprising:
a first layer comprising a dielectric material;
a structure comprising a conductive material over the first layer, wherein the structure comprises a surface roughness of 50 nm or less;
a second layer over the structure, the second layer compositionally distinct from the first layer, wherein the second layer is a single layer conformal with the structure, and wherein the second layer has an uppermost surface above an uppermost surface of the structure;
a third layer over the first layer, the structure, and the second layer, the third layer comprising the dielectric material and compositionally distinct from the second layer;
wherein the structure includes a first portion having a first width and a second portion having a second width that is wider than the first width;
wherein the second portion extends laterally beyond a first side of the first portion by 1 μm to 5 μm, and wherein the second portion extends laterally beyond a second side of the first portion by 1 μm to 5 μm; and
wherein the second layer comprises silicon and one or more of nitrogen, carbon, and oxygen.