US 11,948,895 B2
Semiconductor package structure
Tzu-Hung Lin, Zhubei (TW); Chia-Cheng Chang, Hsinchu (TW); I-Hsuan Peng, Hsinchu (TW); and Nai-Wei Liu, Kaohsiung (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsinchu (TW)
Filed on Jul. 4, 2022, as Appl. No. 17/810,625.
Application 17/810,625 is a continuation of application No. 16/983,182, filed on Aug. 3, 2020, granted, now 11,410,936.
Application 16/983,182 is a continuation of application No. 15/906,098, filed on Feb. 27, 2018, granted, now 10,784,211, issued on Sep. 22, 2020.
Claims priority of provisional application 62/470,915, filed on Mar. 14, 2017.
Prior Publication US 2022/0336374 A1, Oct. 20, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/043 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 23/043 (2013.01); H01L 23/13 (2013.01); H01L 23/3135 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 23/5385 (2013.01); H01L 2224/16227 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor package structure, comprising:
a substrate having a wiring structure;
a first semiconductor die disposed over the substrate and electrically coupled to the wiring structure;
a second semiconductor die disposed over the substrate and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side;
holes formed on a surface of the substrate, wherein the holes are located within a projection of the first semiconductor die or the second semiconductor die on the substrate; and
a molding material, surrounding the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate are exposed by the molding material.