US 11,948,842 B2
Etch stop layer between substrate and isolation structure
Ming-Chang Wen, Kaohsiung (TW); Chang-Yun Chang, Taipei (TW); Hsien-Chin Lin, Hsinchu (TW); and Hung-Kai Chen, Taichung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 26, 2021, as Appl. No. 17/240,007.
Application 16/690,177 is a division of application No. 15/816,155, filed on Nov. 17, 2017, granted, now 10,978,351, issued on Apr. 13, 2021.
Application 17/240,007 is a continuation of application No. 16/690,177, filed on Nov. 21, 2019, granted, now 10,991,628.
Prior Publication US 2021/0242090 A1, Aug. 5, 2021
Int. Cl. H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/823481 (2013.01) [H01L 21/762 (2013.01); H01L 21/76229 (2013.01); H01L 21/823431 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a substrate;
semiconductor fins extending from the substrate;
a liner layer on sidewalls of the semiconductor fins;
an etch stop layer over the substrate and extending laterally from a first portion of the liner layer on a first one of the semiconductor fins to a second portion of the line layer on a second one of the semiconductor fins;
an isolation structure over the etch stop layer, wherein the etch stop layer and the isolation structure include different materials;
a gate dielectric layer over a top surface of the isolation structure; and
a dielectric feature extending through the gate dielectric layer and into the isolation structure, wherein the isolation structure and the dielectric feature collectively extend laterally from the first portion of the liner layer to the second portion of the line layer.