US 11,948,834 B2
Selective deposition of barrier layer
Hsin-Yen Huang, New Taipei (TW); Hai-Ching Chen, Hsinchu (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Feb. 14, 2022, as Appl. No. 17/671,222.
Application 17/671,222 is a continuation of application No. 16/837,968, filed on Apr. 1, 2020, granted, now 11,251,073.
Prior Publication US 2022/0165613 A1, May 26, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01)
CPC H01L 21/76816 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02172 (2013.01); H01L 21/0228 (2013.01); H01L 21/30604 (2013.01); H01L 21/31116 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature over the first ILD layer;
forming a hard mask layer directly on the first metal feature, the hard mask having a top surface facing away from the semiconductor substrate;
depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer and the top surface of the hard mask layer; and
depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the first metal feature relative to the first ILD layer and the hard mask layer.