US 11,948,798 B2
Semiconductor device and method
Ching-Yu Chang, Taipei (TW); Jung-Hau Shiu, New Taipei (TW); Jen Hung Wang, Hsinchu (TW); and Tze-Liang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 16, 2021, as Appl. No. 17/377,813.
Application 17/377,813 is a continuation of application No. 16/583,949, filed on Sep. 26, 2019, granted, now 11,069,528.
Claims priority of provisional application 62/753,184, filed on Oct. 31, 2018.
Prior Publication US 2021/0343529 A1, Nov. 4, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/033 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01)
CPC H01L 21/0331 (2013.01) [H01L 21/02167 (2013.01); H01L 21/02211 (2013.01); H01L 21/02214 (2013.01); H01L 21/0228 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing an integrated circuit, the method comprising:
forming a first layer;
forming a first patterned mask, the first patterned mask having a first line pattern and a second line pattern;
forming a second patterned mask over an upper surface of the first patterned mask, the second patterned mask having an opening, the opening exposing a region between the first line pattern and the second line pattern of the first patterned mask;
depositing a first gap-filling material along sidewalls of the opening;
depositing a second gap-filling material over the first gap-filling material within the opening, the second gap-filling material being different from the first gap-filling material;
removing the second patterned mask; and
patterning the first layer using the second gap-filling material as a mask.