US 11,948,635 B2
Memory device current limiter
Chung-Cheng Chou, Hsin-Chu (TW); and Tien-Yen Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 29, 2022, as Appl. No. 17/816,005.
Application 17/816,005 is a continuation of application No. 17/240,534, filed on Apr. 26, 2021, granted, now 11,437,099.
Application 17/240,534 is a continuation of application No. 16/694,114, filed on Nov. 25, 2019, granted, now 10,991,426, issued on Apr. 27, 2021.
Claims priority of provisional application 62/796,864, filed on Jan. 25, 2019.
Prior Publication US 2022/0366980 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0038 (2013.01) [G11C 13/0026 (2013.01); G11C 13/003 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array including a plurality of memory cells arranged in rows and columns;
a current limiter coupled to a plurality of the columns of the memory array and comprising a cascode of first and second connected NMOS transistors;
a closed loop bias generator comprising third and fourth cascode connected NMOS transistors, the closed loop bias generator configured to output a column select signal to the memory array that is received by the current limiter; and
an operational amplifier configured to receive a feedback signal and generate a column select signal output to a column MUX, wherein the output of the operational amplifier is connected to a gate of the first NMOS transistor, and a source of the third NMOS transistor is connected to a gate of the second NMOS transistor.