US 11,948,627 B2
Static random access memory with write assist circuit
Hidehiro Fujiwara, Hsinchu (TW); Chih-Yu Lin, Taichung (TW); Sahil Preet Singh, Hsinchu (TW); Hsien-Yu Pan, Hsinchu (TW); Yen-Huei Chen, Hsinchu (TW); and Hung-Jen Liao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/818,386.
Application 17/818,386 is a continuation of application No. 16/983,749, filed on Aug. 3, 2020, granted, now 11,423,977.
Application 16/983,749 is a continuation of application No. 15/800,443, filed on Nov. 1, 2017, granted, now 10,734,066, issued on Aug. 4, 2020.
Claims priority of provisional application 62/538,259, filed on Jul. 28, 2017.
Prior Publication US 2022/0383947 A1, Dec. 1, 2022
Int. Cl. G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 7/12 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); H03K 19/013 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 5/147 (2013.01); G11C 7/12 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); H03K 19/0136 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first capacitive element;
a second capacitive element; and
a logic circuit configured to:
receive row address information associated with first memory cells in a first portion of a memory region and with second memory cells in a second portion of the memory region; and
control a reference voltage provided to first bitlines coupled to the first memory cells in the first portion of the memory region and second bitlines coupled to the second memory cells coupled to the second memory cells in the second portion of the memory region,
wherein the second bitlines are longer than the first bitlines,
wherein, in response to the row address information being associated with at least one of the first memory cells, the logic circuit is configured to couple, via the first capacitive element, the reference voltage to a first negative voltage applied to the first bitlines coupled to the first memory cells in the first portion of the memory region,
wherein, in response to the row address information being associated with at least one of the second memory cells, the logic circuit is configured to couple, via the first and second capacitive elements, the reference voltage to a second negative voltage lower than the first negative voltage, and
wherein the second negative voltage is applied to the second bitlines coupled to the second memory cells in the second portion of the memory region.