US 11,948,622 B2
Generating access line voltages
Martin Brox, Munich (DE); C. Omar Benitez, Meridian, ID (US); Johnathan L. Gossi, Boise, ID (US); and Christopher John Kawamura, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 15, 2022, as Appl. No. 17/659,405.
Prior Publication US 2023/0335179 A1, Oct. 19, 2023
Int. Cl. G11C 11/40 (2006.01); G11C 5/14 (2006.01); G11C 11/22 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4085 (2013.01) [G11C 5/14 (2013.01); G11C 11/2259 (2013.01); G11C 11/4094 (2013.01); G11C 11/221 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A method, comprising:
activating a first circuit to couple a node with a first voltage supply for supplying voltage to a set of word lines in a memory array, the node coupled with a set of digit lines in the memory array;
applying a first voltage to the set of digit lines based at least in part on activating the first circuit, the first voltage based at least in part on a voltage output by the first voltage supply;
activating a second circuit to couple the node with a second voltage supply for supplying voltage to peripheral circuitry; and
applying a second voltage to the set of digit lines based at least in part on activating the first circuit, the second voltage based at least in part on a voltage output by the second voltage supply.