US 11,948,621 B2
Memory devices, memory systems having the same, and operating methods thereof
Jaewoo Jeong, Daejeon (KR); Yonghun Kim, Hwaseong-si (KR); Jaemin Choi, Suwon-si (KR); Yoochang Sung, Hwaseong-si (KR); and Changsik Yoo, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 14, 2022, as Appl. No. 17/839,639.
Claims priority of application No. 10-2021-0099467 (KR), filed on Jul. 28, 2021; application No. 10-2021-0168429 (KR), filed on Nov. 30, 2021; and application No. 10-2022-0023402 (KR), filed on Feb. 23, 2022.
Prior Publication US 2023/0035176 A1, Feb. 2, 2023
Int. Cl. G11C 11/4076 (2006.01)
CPC G11C 11/4076 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first rank having first memory banks and a first quad skew adjustment circuit; and
a second rank having second memory banks and a second quad skew adjustment circuit,
wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to:
receive a 4-phase clock through first channels;
detect internal quad skew of the 4-phase clock;
correct skew of the 4-phase clock according to the detected quad skew; and
output mode register information corresponding to the detected quad skew through a second channel.