US 11,948,618 B2
Non-volatile analog resistive memory cells implementing ferroelectric select transistors
Nanbo Gong, White Plains, NY (US); and Takashi Ando, Eastchester, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 12, 2023, as Appl. No. 18/133,867.
Application 18/133,867 is a division of application No. 17/563,687, filed on Dec. 28, 2021, granted, now 11,727,977.
Application 17/563,687 is a division of application No. 17/119,350, filed on Dec. 11, 2020, granted, now 11,232,824, issued on Jan. 25, 2022.
Prior Publication US 2023/0274773 A1, Aug. 31, 2023
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/2275 (2013.01) [G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2273 (2013.01); G11C 11/2297 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising programming a non-volatile analog resistive memory cell which comprises a ferroelectric field-effect transistor (FeFET) device and a resistive memory device coupled to the FeFET device, wherein programming the non-volatile analog resistive memory cell comprises applying a sequence of programming pulses to the non-volatile analog resistive memory cell for modulating a polarization state of the FeFET device and affecting a linear response in a conductance tuning of the resistive memory device in response to modulating the polarization state of the FeFET device.