US 11,948,616 B2
Semiconductor structure and manufacturing method thereof
Xiaoguang Wang, Hefei (CN); Dinggui Zeng, Hefei (CN); Huihui Li, Hefei (CN); Jiefang Deng, Hefei (CN); and Kanyu Cao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed on Jun. 23, 2022, as Appl. No. 17/808,404.
Application 17/808,404 is a continuation of application No. PCT/CN2022/078678, filed on Mar. 1, 2022.
Claims priority of application No. 202111338280.3 (CN), filed on Nov. 12, 2021.
Prior Publication US 2023/0154515 A1, May 18, 2023
Int. Cl. G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC G11C 11/161 (2013.01) [G11C 11/1655 (2013.01); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a transistor, comprising a control terminal, a first terminal, and a second terminal, wherein the first terminal and the second terminal are located in the substrate, and the control terminal is located between the first terminal and the second terminal;
a first magnetic memory structure, wherein a bottom electrode of the first magnetic memory structure is electrically connected to the first terminal of the transistor;
a second magnetic memory structure, wherein a top electrode of the second magnetic memory structure is electrically connected to the first terminal of the transistor, and the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure;
a first bit line, electrically connected to a top electrode of the first magnetic memory structure;
a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and
a selection line, electrically connected to the second terminal of the transistor.