CPC G09G 3/3291 (2013.01) [G09G 3/2074 (2013.01); G09G 2300/0452 (2013.01); G09G 2310/027 (2013.01); G09G 2320/0626 (2013.01); G09G 2320/0673 (2013.01); G09G 2330/028 (2013.01)] | 19 Claims |
1. A source driver, comprising a first digital-to-analog converter (DAC) and a second DAC, the first DAC being in a first driving channel for driving a first-color subpixel and the second DAC being in a second driving channel for driving a second-color subpixel, each of the first DAC and the second DAC being configured to output at least one output voltage according to an N-bit data code, and each of the first DAC and the second DAC comprising: a plurality of sub-DACs, wherein each of the sub-DACs is configured to receive m bits of the N-bit data code and generate a set of intermediate voltages according to the m bits of the N-bit data code; an interpolation circuit, configured to perform an interpolation on a selected set of intermediate voltages according to k bits of the N-bit data code and at least one interpolation control signal, to generate the at least one output voltage; and a switch circuit, coupled to the plurality of sub-DACs and the interpolation circuit, and configured to, according to a first select signal and a second select signal, electrically connect the interpolation circuit and a selected sub-DAC among the plurality of sub-DACs which outputs the selected set of intermediate voltages, wherein the interpolation circuit of the first DAC and the interpolation circuit of the second DAC respectively perform the interpolation on the respective selected set of intermediate voltages according to different numbers of interpolation bits, wherein the at least one output voltage is output to an output buffer, which is configured to output a data voltage according to the at least one output voltage.
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