US 11,948,017 B2
Thread modification to reduce command conversion latency
Abhishek Venkatesh, Bengaluru (IN); Michael Apodaca, Folsom, CA (US); Stav Gurtovoy, Folsom, CA (US); John H. Feit, Folsom, CA (US); Mateusz Przybylski, Folsom, CA (US); and David M. Cimini, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 8, 2020, as Appl. No. 16/896,031.
Prior Publication US 2021/0382765 A1, Dec. 9, 2021
Int. Cl. G06F 9/44 (2018.01); G06F 9/54 (2006.01); G06T 1/20 (2006.01)
CPC G06F 9/542 (2013.01) [G06F 9/546 (2013.01); G06T 1/20 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A graphics processing apparatus comprising:
a memory device; and
a central processing unit (CPU), the CPU configured to:
execute a producer code segment to issue graphics command application program interfaces (APIs) to a queue in the memory device;
execute a driver to translate graphics command APIs of the queue of graphics command APIs into graphics processing unit (GPU) executable instructions;
based on an idle state of the producer code segment, change operation of the producer code segment to execute a command translation code segment of the producer code segment to perform operations of the driver to translate an allocated number of graphics command APIs from the queue of graphics command APIs into GPU executable instructions, wherein the allocated number is based on a number of unexecuted graphics command APIs in the queue; and
based on completion of the operations of the producer code segment to translate the allocated number of graphics command APIs from the queue of graphics command APIs into GPU executable instructions, cause the producer code segment to return to performance of issuance of graphics command APIs to the queue in the memory device.