CPC G06F 9/4498 (2018.02) [G06F 13/126 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G06F 13/38 (2013.01); G06F 13/4282 (2013.01)] | 22 Claims |
1. A system, comprising:
a processor;
a plurality of devices arranged in a rank; and
a direct memory access (DMA) controller coupled to the processor and the plurality of devices, wherein the processor is configured to determine variable data length portions of a data stream for transfer between the DMA controller and at least one device of the plurality of devices and structure DMA transfers between the DMA controller and the at least one device of the plurality of devices as having variable data lengths based on the variable data length portions of the data stream, wherein the processor is configured to structure a size of DMA transfers from the plurality of devices to the DMA controller as corresponding to a greatest buffer byte count received from the plurality of devices.
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