US 11,947,979 B2
Systems and devices for accessing a state machine
Harold B Noyes, Boise, ID (US); David R. Brown, Lucas, TX (US); and Paul Glendenning, Woodside, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 4, 2022, as Appl. No. 17/736,399.
Application 17/736,399 is a continuation of application No. 16/525,187, filed on Jul. 29, 2019, granted, now 11,366,675.
Application 16/525,187 is a continuation of application No. 15/534,978, granted, now 10,430,210, issued on Oct. 1, 2019, previously published as PCT/US2015/067914, filed on Dec. 29, 2015.
Claims priority of provisional application 62/098,165, filed on Dec. 30, 2014.
Prior Publication US 2022/0261257 A1, Aug. 18, 2022
Int. Cl. G06F 13/16 (2006.01); G06F 9/448 (2018.01); G06F 13/12 (2006.01); G06F 13/28 (2006.01); G06F 13/38 (2006.01); G06F 13/42 (2006.01)
CPC G06F 9/4498 (2018.02) [G06F 13/126 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G06F 13/38 (2013.01); G06F 13/4282 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A system, comprising:
a processor;
a plurality of devices arranged in a rank; and
a direct memory access (DMA) controller coupled to the processor and the plurality of devices, wherein the processor is configured to determine variable data length portions of a data stream for transfer between the DMA controller and at least one device of the plurality of devices and structure DMA transfers between the DMA controller and the at least one device of the plurality of devices as having variable data lengths based on the variable data length portions of the data stream, wherein the processor is configured to structure a size of DMA transfers from the plurality of devices to the DMA controller as corresponding to a greatest buffer byte count received from the plurality of devices.