US 11,947,888 B2
Semiconductor processing tools with improved performance by use of hybrid learning models
Stephen Moffatt, St. Brelade (JE); Sheldon R. Normand, Santa Clara, CA (US); and Dermot P. Cantwell, Sunnyvale, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Jan. 19, 2023, as Appl. No. 18/099,130.
Application 18/099,130 is a continuation of application No. 16/944,012, filed on Jul. 30, 2020, granted, now 11,586,794.
Prior Publication US 2023/0153503 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/367 (2020.01); G06F 30/398 (2020.01); H01L 21/66 (2006.01)
CPC G06F 30/367 (2020.01) [G06F 30/398 (2020.01); H01L 22/20 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for developing a semiconductor manufacturing process recipe, comprising:
selecting one or more device outcomes;
querying a hybrid model to obtain a process recipe recommendation suitable for obtaining the device outcomes, wherein the hybrid process model comprises:
a statistical model; and
a physical model, wherein the physical model is generated from a simulation of physical and chemical interactions within a processing tool across a plurality of different processing parameters;
executing a design of experiment (DoE) on a set of wafers to validate the process recipe recommended by the hybrid process model and to provide a validated process recipe;
applying the validated process recipe to a wafer;
executing the recipe on a plurality of first wafers;
obtaining wafer data from the plurality of first wafers;
obtaining process data from the processing tool relating to the execution of the recipe on the plurality of first wafers; and
providing the wafer data and the process data from the processing of the plurality of first wafers to the hybrid model to generate an updated hybrid model.