US 11,947,810 B2
Semiconductor memory device and memory system including the same
Sungrae Kim, Seoul (KR); Hyeran Kim, Uiwang-si (KR); Myungkyu Lee, Seoul (KR); Chisung Oh, Suwon-si (KR); Kijun Lee, Seoul (KR); Sunghye Cho, Hwaseong-si (KR); and Sanguhn Cha, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 12, 2022, as Appl. No. 17/743,137.
Claims priority of application No. 10-2021-0069726 (KR), filed on May 31, 2021.
Prior Publication US 2022/0382464 A1, Dec. 1, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines; and
a cyclic redundancy check (CRC) engine configured to perform, during a memory operation on the memory cell array, operations comprising:
detecting an error in a main data and a system parity data received from a memory controller through a link, wherein the memory controller is external to the semiconductor memory device;
generating an error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data; and
transmitting the error flag to the memory controller.