CPC G06F 13/3625 (2013.01) [G06F 1/12 (2013.01); G06F 13/4004 (2013.01); G06F 13/423 (2013.01); H04L 7/0037 (2013.01)] | 20 Claims |
1. An internal delay correction circuit, comprising:
an input connected with a line of a bus, wherein the line of the bus is used for time-multiplexed clock and data communication;
a time-gate that filters data traffic on the line of the bus from synchronization pulses;
a plurality of delay cells;
a bus synchronization circuit that controls the plurality of delay cells;
a multiplexer that is used to control output timing using the plurality of delay cells; and
an output connected with the line of the bus, wherein the output timing controlled by the multiplexer controls timing of data output via the output.
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