US 11,947,477 B2
Shared buffer for multi-output display systems
Anish Reghunath, Allen, TX (US); Brian Chae, Duluth, GA (US); Jay Scott Salinger, Framingham, MA (US); and Chunheng Luo, Dallas, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 15, 2022, as Appl. No. 17/887,906.
Application 17/887,906 is a continuation of application No. 16/704,820, filed on Dec. 5, 2019, granted, now 11,436,171.
Application 16/704,820 is a continuation of application No. 16/237,388, filed on Dec. 31, 2018, granted, now 10,534,736, issued on Jan. 14, 2020.
Prior Publication US 2022/0391338 A1, Dec. 8, 2022
Int. Cl. G06F 12/02 (2006.01); G06F 3/14 (2006.01); G06F 12/1081 (2016.01); G06F 13/28 (2006.01)
CPC G06F 13/28 (2013.01) [G06F 3/14 (2013.01); G06F 12/1081 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a direct memory access (DMA) engine; and
a buffer coupled to the DMA engine and comprising a memory space allocated to store data that is received from the DMA engine and is to be processed by a thread that comprises a first channel and a second channel to process respectively a first portion of the data and a second portion of the data, and wherein the memory space comprises a first memory space and a second memory space allocated to store respectively the first portion of the data for the first channel and the second portion of the data for the second channel,
wherein the DMA engine is configured to:
receive a request to adjust a size of the first memory space; and
in response to the request,
adjust the size of the first memory space; and
adjust a size of the second memory space based on the adjustment of the size of the first memory space.