US 11,947,473 B2
Duplicated registers in chiplet processing units
Haikun Dong, Beijing (CN); Kostantinos Danny Christidis, Toronto (CA); Ling-Ling Wang, Santa Clara, CA (US); MinHua Wu, Shanghai (CN); Gaojian Cong, Shanghai (CN); and Rui Wang, Shanghai (CN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Oct. 12, 2021, as Appl. No. 17/499,494.
Prior Publication US 2023/0115819 A1, Apr. 13, 2023
Int. Cl. G06F 13/16 (2006.01); G06F 3/06 (2006.01)
CPC G06F 13/1673 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first control unit in a first semiconductor die of a plurality of semiconductor dies, wherein the first control unit comprises circuitry configured to:
receive register accesses from at least a first initiator in the first semiconductor die and, via a communication link, register accesses from at least a second initiator in a second semiconductor die of the plurality of semiconductor dies;
in response to receiving a given register access, determine which copy of a targeted register to access so as to fulfill the given register access;
perform the given register access to a first copy of the targeted register responsive to determining the first initiator generated the given register access; and
perform the given register access to a second copy of the targeted register responsive to determining the second initiator generated the given register access, wherein the second copy is different from the first copy.