US 11,947,458 B2
Using cache coherent FPGAS to track dirty cache lines
Irina Calciu, Palo Alto, CA (US); Jayneel Gandhi, Sunnyvale, CA (US); Aasheesh Kolli, Palo Alto, CA (US); and Pratap Subrahmanyam, Saratoga, CA (US)
Assigned to VMware, Inc., Palo Alto, CA (US)
Filed by VMware LLC, Palo Alto, CA (US)
Filed on Jul. 27, 2018, as Appl. No. 16/048,180.
Prior Publication US 2020/0034297 A1, Jan. 30, 2020
Int. Cl. G06F 12/0817 (2016.01)
CPC G06F 12/0828 (2013.01) [G06F 2212/152 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for tracking dirtiness of data in memory, the method comprising:
monitoring cache coherence events, for a cache, occurring on a coherence interconnect that is connected to monitoring hardware comprising a memory and processing hardware, the processing hardware including the cache;
receiving, based on the monitoring, a write back transaction in which a modified cache line is written back from the cache to the memory;
determining, based on the write back transaction, that data in a page of the memory is dirty, wherein the data is of a fixed size corresponding to a size of a cache line of the cache;
adding, based on the write back transaction, a representation of the data to a buffer to indicate that the data in the page of the memory is dirty; and
based on determining that that the data in the page of the memory is dirty, copying the data in the page of the memory from a source computer to a destination computer without copying other data in the page that is different from the data of the fixed size corresponding to the size of the cache line.