US 11,947,420 B2
Hardware memory error tolerant software system
Jue Wang, Redmond, WA (US); and Daniel Ryan Vance, Seattle, WA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/551,767.
Prior Publication US 2023/0185663 A1, Jun. 15, 2023
Int. Cl. G06F 11/14 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G06F 12/0882 (2016.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 12/0238 (2013.01); G06F 12/0882 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A hardware memory error tolerant software system, comprising:
one or more processing devices;
an input for receiving information indicating memory locations at which hardware memory errors are detected; and
a memory storing instructions that cause the one or more processing devices to:
instantiate a kernel agent in response to one or more requests to access memory, the kernel agent determining based on the received information whether the request to access memory will cause access to a corrupt memory location,
skip an operation associated with the corrupt memory location in response to a determination that the request will access the corrupt memory location,
wherein the request to access memory comprises a request to access a page in memory, and
wherein the instructions cause the one or more processing devices to skip an operation associated with the page in response to the determination that the request will access the corrupt memory location.